Microelectronic imaging devices include semiconductor dies having image sensors located on a front surface of the die to receive incoming radiation. The dies also include external contacts or terminals for electrically coupling the sensors to other circuit elements. To prevent the external contacts from interfering with the operation of the sensors or limiting the size and/or location of the sensors, the external contacts at the front surface can be electrically coupled to corresponding external contacts on the back surface of the die by internal interconnects. The internal interconnects can be through-substrate vias (TSVs). The TSVs are formed by (a) making through holes or blind holes in the die that are aligned with the corresponding external contacts, (b) lining the sidewalls of the openings with a dielectric material, and (c) at least partially filling the openings with a conductive material. External interconnect elements such as solder balls or wirebonds can then be attached to the external contacts on the backside to couple the die to external devices.
FIGS. 1A-1D illustrate a process for forming an infrared radiation (IR) blocking layer on a backside of an imager 10 using two separate photo-lithography processes. FIG. 1A illustrates the imager 10 being formed on a microfeature workpiece 100 having a substrate 101 with a front side 103 and a backside 105, a dielectric layer 102 with a first surface 104 and a second surface 106, and a plurality of holes 108 with dielectric liners 109. The imager 10 also has an image sensor 107a at the front side 103 of the substrate 101, integrated circuitry 107b on and/or in the substrate 101, and bond pads 110 at the front side 103. The workpiece 100 also has a conductive redistribution structure 111 having traces 112 on the first surface 104 of the dielectric layer 102, interconnects 114 in the holes 108, and ball-pads 116 at or near the end of respective traces 112.
To form an IR blocking layer over the backside 105 of the substrate 101 and the conductive redistribution structure 111, two separate photo-lithography processes are performed. FIG. 1B illustrates a first photo-lithography process in which a photo-definable IR blocking layer 118 is applied the workpiece 100 to cover the conductive redistribution structure 111 and the exposed portions of the dielectric layer 102. The IR blocking layer 118 is typically applied using a conventional spin-on process in which a liquid IR blocking material is deposited onto the workpiece and the workpiece is rotated to spread the liquid IR blocking material. A first photo-lithography process is performed to pattern openings 119 through the IR blocking layer 118. At the same time the material inside the via may or may not be removed. The openings 119 are patterned such that they expose the ball-pads 116 as shown in FIG. 1C. The IR blocking material is then cured or hardened. FIG. 1C shows the IR blocking material inside the via.
After the ball-pads 116 are exposed, a photoreactive passivation layer 120 is applied to the IR blocking layer 118 as shown in FIG. 1D. The passivation layer 120 is typically a preformed dry resist film positioned on the workpiece in a vacuum environment. The vacuum is then released to pull the passivation layer 120 into the holes 108. The passivation layer may line the hole as shown in FIG. 1D, or it can completely fill the hole. After depositing the passivation layer 120, a second photo-lithography process is performed to form openings 121 in the passivation layer 120 aligned with the ball-pads 116. After the openings 121 are formed, a solder ball or other external connector may be attached to the ball-pads 116.
One drawback of the method shown in FIGS. 1A-1D is that two separate photo-lithography processes are required. Photo-lithography equipment is expensive, and the process of applying, exposing, and developing the layers of IR blocking material and passivation material to form the openings 119 and 120 can be time consuming. As such, the method described with respect to FIGS. 1A-1D is capital intensive and expensive to perform.
Another drawback of the method shown in FIGS. 1A-1D is that photo-patterned IR blocking layers may not adequately block infrared radiation. This problem occurs because spin-on processes may not uniformly coat topographic structures, such as deep holes for through-substrate interconnects, with the liquid IR blocking material. As a result, it is generally desirable to deposit a thick layer of IR blocking material using conventional spin-on processes to adequately cover the surface of the wafer with the IR blocking material. However, because IR blocking material blocks radiation, the IR blocking layer cannot be too thick or else the radiation of the photo-patterning process will not penetrate through the full thickness of the IR blocking layer. Conventional IR blocking layers in microelectronic imagers are accordingly susceptible to allowing infrared radiation to pass through the blocking layer to the imager.
A further drawback of the method described in FIGS. 1A-1D is that photo-definable materials are relatively more expensive than equivalent materials that are not photo-definable. As a result, in addition to the cost of the photo-patterning tool, photo-definable IR blocking layers are relatively expensive.